The present disclosure relates to a semiconductor device and a method of manufacturing the same, and relates to, for example, a semiconductor device including a deep well and a method of manufacturing the same.
Japanese Unexamined Patent Application Publication Nos. 2009-272552 and 2009-194369 each disclose a semiconductor device including an N-type deep well (this well is referred to as a deep N-well) formed in a P-type semiconductor substrate. The semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2009-272552 moves electric charges accumulated in the deep N-well in a manufacturing process to the semiconductor substrate using a diffusion tap.
Specifically, a P-type shallow well (this well is referred to as a shallow P-well) and an N-type shallow well (this well is referred to as a shallow N-well) are formed on the deep N-well. Further, a shallow P-well and a shallow N-well are formed in a region on the semiconductor substrate other than the region in which the deep N-well is formed. A P-type diffusion tap is formed in the shallow P-well on the side of the semiconductor substrate. The P-type diffusion tap is also formed in the shallow P-well on the side of the deep N-well. Then the diffusion taps are connected to each other.
Next, an N-type MOS transistor (this transistor is referred to as an NMOS) is formed in the shallow P-well on the side of the deep N-well, and a P-type MOS transistor (this transistor is referred to as a PMOS) is formed in the shallow N-well. An NMOS is formed in the shallow P-well on the side of the semiconductor substrate, and a PMOS is formed in the shallow N-well on the side of the semiconductor substrate. Then drain electrodes of the NMOS and the PMOS on the side of the deep N-well and gate electrodes of the NMOS and the PMOS on the side of the semiconductor substrate are connected to each other using a wire provided above the connection of the diffusion taps.
Accordingly, the electric charges accumulated in the deep N-well move to the side of the semiconductor substrate due to the connection of the diffusion taps before the gate electrode of the NMOS and the gate electrode of the PMOS on the side of the semiconductor substrate are connected to each other.
As described above, the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2009-272552 moves the electric charges accumulated in the deep N-well toward the semiconductor substrate, thereby preventing gate breakdown of the NMOS and the PMOS on the side of the semiconductor substrate.
Japanese Unexamined Patent Application Publication No. 2009-194369 discloses using an inverter circuit formed on a deep N-well as a method of moving electric charges accumulated in the deep N-well in a manufacturing process to a semiconductor substrate. The semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2009-194369 moves the electric charges accumulated in the deep N-well to the semiconductor substrate via a channel formed in the transistor of the inverter circuit.
As described above, the semiconductor devices disclosed in Japanese Unexamined Patent Application Publication Nos. 2009-272552 and 2009-194369 move the electric charges accumulated in the deep N-well to the semiconductor substrate and suppress gate breakdown of the NMOS and the PMOS.